1. Field of the Invention
The present invention relates to a fuse circuit, and more particularly, to a fuse circuit which can operate in either normal mode or test mode.
2. Description of the Related Art
Modern integrated circuits such as Dynamic Random Access Memory (DRAM) often require multiple internal voltages to be applied to the integrated circuit. However, such supply voltages often fluctuate due to variations in temperature, the fabrication process, or positioning of chips on the wafer. To minimize the variation in response to the external factors, fuses are often utilized to control the voltage levels.
FIG. 1 shows a conventional fuse circuit 10 in which a fuse R1 is connected to a PMOS transistor P1, an NMOS transistor N1, and a latch circuit 12. The latch circuit 12 is composed of inverters X1 and X2. The operation of the fuse circuit 10 is illustrated below. When a supply voltage VCC rises from 0 volt to a predetermined voltage level, a power up signal PU applied to a PMOS transistor P1 is at a logic low level and thus the latch circuit 12 sends a logic low signal from its output node F. When the supply voltage VCC reaches the predetermined voltage level, the power up signal PU switches from logic low level to logic high level, rendering the PMOS transistor P1 non-conductive. Therefore, the voltage at node F is determined according to a conductivity state of the fuse R1. If the fuse R1 is blown and changes to an open state, the voltage at node F remains the previous logic low level. Otherwise, the voltage at node F changes to a logic high level since the fuse R1 is not blown and the transistor N1 is turned on.
The voltage at node F is then sent to a decoder (not shown). The decoder serves to decode signals from a plurality of fuse circuits for generating a plurality of trim bits, wherein the trim bits serve to adjust the level of reference voltages in response to changes in the external environment. Therefore, by improving the voltage variation of the reference voltages, the yield can be remarkably increased.
However, in the conventional fuse circuit 10, after the voltage at node F is activated by blowing the fuse R1, the voltage at node F cannot be reverted again. In the conventional configuration, there is a shortcoming that the device cannot perform the function of the test mode after the fuse is blown. FIG. 2 shows a fuse disposing circuit 20 disclosed in U.S. Pat. No. 7,395,475, wherein the fuse disposing circuit 20 can operate in either normal mode or test mode. The circuit 20 comprises a test mode enable confirmation section 230, a plurality of fuse sets 210a, 210b, 210c, and a decoder 220. The test mode enable confirmation section 230 sends a signal tm_enb to the fuse sets 210a-210c when the test mode is enabled. Each of the fuse sets 210a-210c further comprises a comparison circuit (not shown) to render the output of the circuit 20 at a constant logic level regardless of whether the fuse is blown in the test mode. Because the comparison circuit is required for each of the fuse sets, the semiconductor chip is area-consuming and the cost of manufacturing the semiconductor chip is high.
Therefore, there is a need to provide a fuse circuit which can operate in either normal mode or test mode.